1. Field of the Invention
The invention relates generally to non-volatile memory devices, and in particular to flash memory and manufacturing of flash memory devices.
2. Description of Related Art
Flash memory technology includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold of the transistor, and the changes in threshold due to the stored charge can be sensed to indicate data.
One type of charge storage memory cell in widespread application is known as a floating gate memory cell. In a floating gate memory cell, a floating gate of conductive material such as polysilicon is formed over a tunneling barrier structure, and an interpoly dielectric is formed over the floating gate to isolate it from the wordline or control gate of the memory cell. The geometry of the floating gate is engineered to establish a high coupling ratio for a voltage between the floating gate and channel, so that a voltage applied on the control gate will result in a stronger electric field across the tunneling barrier structure. For example, floating gates are implemented using a T-shape or a U-shape, which results in a greater surface area between the control gate and the floating gate than between the floating gate and the channel, and thereby a greater capacitance between the floating gate and the control gate. Although this technology has been widely successful, as the sizes of the memory cells and the distances between them shrink, the floating gate technology starts to degrade because of interference between neighboring floating gates.
Another type of memory cell based on storing charge between the channel and gate of a field effect transistor uses a dielectric charge trapping structure. In this type of memory cell, a dielectric charge trapping structure is formed over a tunneling barrier structure which isolates the dielectric charge trapping structure from the channel, and a top dielectric layer is formed over the charge trapping structure to isolate it from the wordline or gate. A representative device is known as a silicon-oxide-nitride-oxide-silicon SONOS cell.
In memory cells using dielectric charge trapping structures, the device can be planar because there is no coupling ratio engineering involved in the design. Because of the planar structure, and very little coupling between adjacent cells, memory cells using dielectric charge trapping structures are forecast to overtake floating gate memory cells in importance as the minimum feature size for the manufacturing processes goes beyond about 45 nanometers.
It is found that even SONOS-type memory cells can suffer performance degradation as the minimum feature size goes below about 45 nanometers. In particular, non-uniform injection of charge along the channel width in the dielectric charge trapping structure due to the fringing fields can result in a region along the edge of the memory cell with effectively a low threshold voltage, while regions toward the center of the channel have an effectively high threshold. The low threshold region along the edge can result in performance degradation. U.S. patent application Ser. No. 11/756,559, filed 31 May 2007, entitled CHARGE TRAPPING DEVICES WITH FIELD DISTRIBUTION LAYER OVER TUNNELING BARRIER (now US Publication No. 2008-0116506), having the same assignee and same inventor as the present application, describes the combination of a floating gate structure, referred to as a field distribution layer, with a charge trapping layer between the gate and the floating gate structure.
Therefore, it is desirable to maintain a more constant threshold voltage along the channel width dimension even if there is non-uniform charge concentration in the charge trapping structure along the channel width dimension.